The present invention relates to a thin film transistor (hereinbelow abbreviated to TFT) used in an active matrix liquid crystal display device, etc. and in particular to the construction of the TFT useful for preventing an increase in off-level current due to photo-current without increasing the capacitance between the source and the gate.
Heretofore, in order to prevent an increase in off-level current due to photo-current in a TFT using amorphous silicon (hereinbelow abbreviated to a-Si) as a semiconductor layer, there has been adopted a method (1) by which a semiconductor layer pattern is formed dimensioned so as to be enclosed completely inside of a gate electrode pattern, as disclosed in JP-A-No. 60-17962, and a method (2) by which the semiconductor layer is very thin (a layer thickness smaller than 100 nm is chosen) so that light absorbed by the semiconductor layer is reduced as far as possible, in order to prevent generation of the photo-current, as disclosed in JP-A-No. 61-90188, JP-A-No. 61-145869 or JP-A-No. 62-152172.
However, the structure of the TFT disclosed in the prior art method (1) described above gives rise to an increase in the overlapping capacitance between the gate electrode and the source electrode and between the gate electrode and the drain electrode. Such a TFT, in which overlapping capacitance, i.e. stray capacitance, is increased, has not only resulted in the problem of reducing the working speed when it is used as a single device but also another problem that in the case where the TFT is used in an active matrix liquid crystal display panel, scanning signal pulses leak to picture cell (pixel) electrodes and a DC component thereof is applied to the liquid crystal which gives rise to a burning phenomena of display pixels. Further, since the semiconductor layer pattern is enclosed (overlapped) completely by the gate electrode pattern, the semiconductor layer pattern is not formed over the step portion at the periphery of the gate electrode pattern. That is, the semiconductor layer pattern doesn't override the step portion of the pattern of the gate electrode. For this reason, this TFT has a drawback that an interlayer short circuit and an increase in leak current between the gate electrode and the source electrode or between the gate electrode and the drain electrode may likely develop with respect to a TFT having a structure, in which the semiconductor layer pattern overrides the step portion of the pattern of the gate electrode, i.e. a structure, in which the semiconductor layer is formed so as to override the step portion of the gate electrode pattern. As described above, the TFT according to the prior art technique (1) has a problematical point, when an application thereof in an active matrix liquid crystal display is considered.
On the other hand the prior art method (2) described above is a method, by which the thickness of the semiconductor layer made of e.g. hydrogenated amorphous silicon (hereinbelow abbreviated to a-Si:H(i)) is reduced to a very small value, which is as small as several tens of nm. In this way the amount of light absorbed by the a-Si:H(i) layer is reduced and thus the number of generated photo-carriers is decreased. As a result, it is possible to suppress increase in the off level current in the TFT due to irradiation with light. Usually, when the thickness of the a-Si:H(i) layer falls below 100 nm, the suppression of the off level current begins to take effect and when this thickness is reduced to a value of about 15 to 20 nm, the off level current is decreased to a value, which is so small that irradiation thereof with light of about 50,000 lx gives rise to no problem (about 10.sup.12 .OMEGA. calculated in terms of the off resistance). However, for fabricating a TFT using an a-Si:H(i) layer of about 15 to 20 nm, there is a problem in fabrication steps therefor. That is, when the thickness t of the a-Si:H(i) layer is considerably small, it is difficult to have a margin in view of the fabrication process and therefore there is a problem that fabrication yield is lowered.
In order to remove the problematical points described above, there is known a method as disclosed in JP-A-No. 61-90188, JP-A-No. 61-145869 and JP-A-No. 62-152172, by which an SiN gate insulating layer, a very thin a-Si:H(i) layer and an SiN channel protecting layer are formed one after another by the plasma CVD method; after having etched selectively the SiN channel protecting layer by the photolithographic method, an a-Si:H(n.sup.+) layer is deposited again by the plasma CVD method; and then a TFT is formed by forming island-shaped patterns of a-Si:H(i) and (n.sup.+) forming the source and the drain electrodes and etching the channel portion of the a-Si:H(n.sup.+). According to this method, since the a-Si:H(n.sup.+) on the SiN channel protecting layer, even if it is overetched, the a-Si:H(i) layer is not influenced. However, this method has drawbacks in that the fabrication steps are lengthened and as a result thereof there is a rise in the production cost.